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MCM69Q536 32K x 36 Bit Synchronous Separate I/O SRAM

MCM69Q536 Description

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69Q536/D Advance Information MCM69Q536 32K x 36 Bit Synchronous Separate I/O SRAM.
Pin Locations 55, 57, 59, 61, 63, 65, 68, 70, 72, 74, 76, 143, 145, 167, 169 2, 6, 8, 12, 14, 18, 20, 25, 27, 31, 33, 37, 39, 43, 47, 51, 82, 86, 90,.

MCM69Q536 Features

* separate data input and data output buffers and incorporates input and output registers on board with high speed SRAM. The MCM69Q536 allows the user to perform transparent writes and data pass through. Two data bus ports are provided
* a data input (D) and a data output (Q) port. The synchro

MCM69Q536 Applications

* ATM
* Ethernet Switches
* Cell/Frame Buffers
* SNA Switches Product Family Configurations Part Number Dual Address MCM69D536 MCM69D618 MCM69Q536 MCM69Q618 MCM67Q709 MCM67Q909 n n Single Address Dual I/O Note 1 Note 1 n n n n n n Separate I/O Note 2 Note 2

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Datasheet Details

Part number
MCM69Q536
Manufacturer
Motorola
File Size
183.03 KB
Datasheet
MCM69Q536_MotorolaInc.pdf
Description
32K x 36 Bit Synchronous Separate I/O SRAM

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