MCM72FB8ML Datasheet - Motorola

MCM72FB8ML 256K x 72 Bit Burst RAM Multichip Module

Pin Locations E10 Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate READ, WRITE, or chip deselect cycle. Synchronous Address Status Processor: Active low, interrupts any ongoing bur.

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM72FB8ML/D Advance Information 256K x 72 Bit BurstRAM Multichip Module The 256K x 72 multichip module uses four 4M bit synchronous fast static RAMs designed to provide a burstable, high performance, secondary cache for the PowerPC™ and other high performance microprocessors. It is organized as 256K words of 72 bits each. This device integrates input registers, an output register (MCM72PB8ML only), a 2 bit address counter,.

MCM72FB8ML Features

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* Z High

* Z Write 2, 4 X X X X X X5 READ5 READ READ READ READ READ READ READ READ WRITE WRITE WRITE WRITE WRITE NOTES: 1. X = Don’t Care. 1 = logic high. 0 = logic low. 2. Write is defined as either 1) any SBx and SW low or 2) SGW is low. 3. G is an asynch

MCM72FB8ML Datasheet (252.94 KB)