MPC993 Datasheet - Motorola

MPC993 Dynamic Switch PLL Clock Driver

Pin Name CLK0, CLK0 CLK1, CLK1 Ext_FB, Ext_FB Qa0:1, Qa0:1 Qb0:2, Qb0:2 Inp0bad Inp1bad Clk_Selected Alarm_Reset Sel_Clk Manual_Override PLL_En MR VCCA VCC GNDA GND I/O LVPECL Input LVPECL Input LVPECL Input LVPECL Output LVPECL Output LVCMOS Output LVCMOS Output LVCMOS Output LVCMOS Input LVCMOS I.

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dynamic Switch PLL Clock Driver The MPC993 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 2x, phase aligned clock outputs. External PLL feedback is used to also provide zero delay buffer performan.

MPC993 Features

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MPC993 Datasheet (97.41 KB)