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MPC9992 Datasheet - Motorola

MPC9992 3.3 DIFFRERENTIAL ECL/PECL PLL CLOCK GENERATOR

FA SUFFIX 32 LEAD LQFP PACKAGE CASE 873A The MPC9992 utilizes PLL technology to frequency lock its outputs onto an input reference clock. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC.

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order Number: MPC9992/D Rev 2, 04/2002 Product Preview 3.3V Differential ECL/PECL PLL Clock Generator The MPC9992 is a 3.3 V compatible, PLL based PECL clock driver. Using SiGe technology and a fully differential design ensures optimum skew and PLL jitter performance. The performance of the MPC9992 makes the device ideal for workstation, mainframe computer and telecommunication applications. With output frequencies up to 400 MHz and output skews less than.

MPC9992 Features

* MPC9992 3.3V DIFFERENTIAL ECL/PECL PLL CLOCK GENERATOR

* 7 differential outputs, PLL based clock generator

* SiGe technology supports minimum output skew (max. 150 ps1)

* Supports up to two generated output clock frequencies with a maximum clock frequency up to 400 MHz

MPC9992 Datasheet (143.83 KB)