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MPC9100 DUAL PLL CLOCK GENERATOR

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Description

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual PLL Clock Generator The MPC9100 is a dual PLL phase locked loop clock generator.The device synthesizes a.
Pin Q_31 Q_14 Q_45 VCCO_XX GNDO_XX VCCI GNDI VCCAX GNDAX XTAL1 XTAL2 TCLK FCAPXX FCAPXXP Description 31.

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Datasheet Specifications

Part number
MPC9100
Manufacturer
Motorola
File Size
114.50 KB
Datasheet
MPC9100_Motorola.pdf
Description
DUAL PLL CLOCK GENERATOR

Features

* a fully integrated crystal oscillator as the clock reference source. No external components are required other than the 14.318 MHz crystal. The TCLK input is used only for factory test and cannot be used as the PLL clock reference. To reduce total die area the PLL loop filter capacitors are brought

Applications

* Info section). 2. Inputs have pull
* up resistors which affect input current, PECL_CLK has a pull
* down resistor. AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±0.3V) Symbol tr, tf tpw fXtal tPLZ, tPHZ tPZL tjitter Characteristic Output Rise/Fall Time Output Duty Cycle Crystal Oscill

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