MPC99J93 Datasheet (Motorola) - Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver

MPC99J93, Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver

The MPC99J93 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals.

Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H).

If that CLK is the primary clock, the IDCS will switch to the good secon

MOTOROLA Freescale SEMICONDUCTOR TECHNICAL DATA Semiconductor, Inc.

Order Number: MPC99J93/D Rev 1, 08/2003 Product Preview Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver The MPC99J93 is a PLL clock driver designed specifically for redundant clock tree designs.

The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs.

Two of the output pairs regenerate the input signals frequency and phase while the other three pairs g

MPC99J93 Features

* Fully Integrated PLL MPC99J93 Freescale Semiconductor, Inc FA SUFFIX 32

* LEAD LQFP PACKAGE CASE 873A

* Intelligent Dynamic Clock Switch LVPECL Clock Outputs LVCMOS Control I/O 3.3V Operation 32

* Lead LQFP Packaging Functi