SN74LS112A - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
SN74LS112A Features
* individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the trut
