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UPD44321181 (UPD44321181 / UPD44321361) 32M-BIT ZEROSB SRAM FLOW THROUGH OPERATION

UPD44321181 Description

www.DataSheet4U.com DATA SHEET MOS INTEGRATED CIRCUIT µ PD44321181, 44321361 32M-BIT ZEROSBTM SRAM FLOW THROUGH OPERATION .
The µPD44321181 is a 2,097,152-word by 18-bit and the µPD44321361 is a 1,048,576-word by 36-bit ZEROSB static RAM fabricated with advanced CMOS techno.

UPD44321181 Features

* Low voltage core supply: VDD = 3.3 ± 0.165 V / 2.5 ± 0.125 V
* Synchronous operation
* 100 percent bus utilization
* Internally self-timed write control
* Burst read / write : Interleaved burst and linear burst sequence
* Fully registered inputs and

UPD44321181 Applications

* which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory. ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. Whe

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Datasheet Details

Part number
UPD44321181
Manufacturer
NEC
File Size
318.26 KB
Datasheet
UPD44321181_NEC.pdf
Description
(UPD44321181 / UPD44321361) 32M-BIT ZEROSB SRAM FLOW THROUGH OPERATION

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UPD44321181 UPD44321361 32M-BIT ZEROSB SRAM FLOW THROUGH OPERATION NEC
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