The S7K1636T2M and S7K1618T2M are 18,874,368-bits DDR Common I/O Synchronous Pipelined Burst SRAMs.
They are organized as 524,288 words by 36bits for S7K1636T2M and 1,048,576 words by 18 bits for S7K1618T2M .
Address, data inputs, and all control signals are synchronized to the input clock ( K or K
SSSS7777KKKK1111666613318668TTTT2222MMMM 551122KKxx3366 && 11MMxx1188 DDDDRRIIII++ CCIIOO BBLL22 SSRRAAMM 18Mb DDRII+ CIO BL2 SRAM Specification (2.0 Clock Read Latency) 165FBGA with Pb & Pb Free (ROHS Compliant) NETSOL RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE.
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This document a
S7K1618T2M Features
* 1.8V+0.1V/-0.1V Power Supply.
* DLL circuitry for wide output data valid window and future freguency scaling.
* I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/ -0.1V for 1.8V I/O
* Pipelined, double-data rate operation.
* Common data input/output
Datasheet Details
S7K1618T2M, S7K1636T2M
NETSOL
361.74 KB
512kx36 & 1mx18 ddrii+ cio bl2 sram.
This datasheet PDF includes multiple part numbers: S7K1618T2M, S7K1636T2M.
Please refer to the document for exact specifications by model.
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