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S7K6418T2M Datasheet - NETSOL

S7K6418T2M 2Mx36 & 4Mx18 DDRII+ CIO BL2 SRAM

The S7K6436T2M and S7K6418T2M are 75,497,472-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 2,097,152 words by 36bits for S7K6436T2M and 4,194,304 words by 18 bits for S7K6418T2M . Address, data inputs, and all control signals are synchronized to the input clock ( K or .

SS77KK66443366TT22MM SS77KK66441188TT22MM 22MMxx3366 && 44MMxx1188 DDDDRRIIII++ CCIIOO BBLL22 SSRRAAMM 72Mb DDRII+ CIO BL2 SRAM Specification (2.0 Clock Read Latency) 165FBGA with Pb & Pb Free (ROHS Compliant) NETSOL RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and .

S7K6418T2M Features

* 1.8V+0.1V/-0.1V Power Supply.

* DLL circuitry for wide output data valid window and future freguency scaling.

* I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.

* Pipelined, double-data rate operation.

* Common data input/output

S7K6418T2M Datasheet (400.91 KB)