S7K6418U2M - 2Mx36 & 4Mx18 DDRII+ CIO BL2 SRAM
The S7K6436U2M and S7K6418U2M are 75,497,472-bits DDR Common I/O Synchronous Pipelined Burst SRAMs.
They are organized as 2,097,152 words by 36bits for S7K6436U2M and 4,194,304 words by 18 bits for S7K6418U2M.
Address, data inputs, and all control signals are synchronized to the input clock (K or K)
SSSS7777KKKK6666444413318668UUUU2222MMMM 22MMxx3366 && 44MMxx1188 DDDDRRIIII++ CCIIOO BBLL22 SSRRAAMM 72Mb DDRII+ CIO BL2 SRAM Specification (2.5 Clock Read Latency) 165FBGA with Pb & Pb Free (ROHS Compliant) NETSOL RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only.
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S7K6418U2M Features
* Key Parameters
* 1.8V+0.1V/-0.1V Power Supply.
* DLL circuitry for wide output data valid window and future fre- quency scaling.
* I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O
* Pipelined, double-data rate operation.
* Commo
