S7K6436U2M - 2Mx36 & 4Mx18 DDRII+ CIO BL2 SRAM

Datasheet Details

The S7K6436U2M and S7K6418U2M are 75,497,472-bits DDR Common I/O Synchronous Pipelined Burst SRAMs.

Key Parameters.
1.8V+0.1V/-0.1V Power Supply.
DLL circuitry for wide output data valid window and future fre- quency scaling.
I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
Pipelined, double-data rate operation.
Common data input/output bus.
HSTL I/O.
Full data coherency, providing most current data.
Synchronous pipeline read with self timed late write.
Read latency : 2.5 clo.

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Published: Oct 13, 2018 |