S7K3236T2M Datasheet - NETSOL

S7K3236T2M - 1Mx36 & 2Mx18 DDRII+ CIO BL2 SRAM

The S7K3236T2M and S7K3218T2M are 37,748,736-bits DDR Common I/O Synchronous Pipelined Burst SRAMs.

They are organized as 1,048,576 words by 36bits for S7K3236T2M and 2,097,152 words by 18 bits for S7K3218T2M .

Address, data inputs, and all control signals are synchronized to the input clock ( K or

SS77KK33223366TT22MM SS77KK33221188TT22MM 11MMxx3366 && 22MMxx1188 DDDDRRIIII++ CCIIOO BBLL22 SSRRAAMM 36Mb DDRII+ CIO BL2 SRAM Specification (2.0 Clock Read Latency) 165FBGA with Pb & Pb Free (ROHS Compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO NETSOL PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN NETSOL PRODUCTS OR

S7K3236T2M Features

* 1.8V+0.1V/-0.1V Power Supply.

* DLL circuitry for wide output data valid window and future freguency scaling.

* I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.

* Pipelined, double-data rate operation.

* Common data input/output

S7K3236T2M-NETSOL.pdf