74LVC1G79 Datasheet - NXP Semiconductors

74LVC1G79 Single D-type flip-flop positive-edge trigger

The 74LVC1G79 provides a single positive-edge triggered D-type ﬂip-ﬂop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH transition of the clock pulse. The D-input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Input.

74LVC1G79 Features

* s Wide supply voltage range from 1.65 V to 5.5 V s High noise immunity s Complies with JEDEC standard: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8B/JESD36 (2.7 V to 3.6 V) s ±24 mA output drive (VCC = 3.0 V) s CMOS low power consumption s Latch-up performance exceeds 250 mA s Dir

74LVC1G79_NXPSemiconductors.pdf