* SNR, 62 dBFS; SFDR, 86 dBc Sample rate up to 125 Msps 10-bit pipelined ADC core Clock input divider by 2 for less jitter contribution
* Single 3 V supply
* Flexible input voltage range: 1 V p-p to 2 V p-p
* CMOS or LVDS DDR digital outp
ADC1010S Datasheet (324.46 KB)
ADC1010S
NXP ↗ Semiconductors
324.46 KB
Single 10-bit adc.
ADC1010S series
Rev. 01
* 9 April 2010
www.DataSheet4U.com
Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digit.
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