74ABT5074 Datasheet - NXP

74ABT5074 Synchronizing dual D-type flip-flop

PIN NUMBER 2, 12 3, 11 4, 10 1, 13 5, 9 6, 8 7 14 SYMBOL D0, D1 CP0, CP1 SD0, SD1 RD0, RD1 Q0, Q1 Q0, Q1 GND VCC NAME AND FUNCTION Data inputs Clock inputs (active rising edge) Set inputs (active-Low) Reset inputs (active-Low) Data outputs (active-Low), non-inverting Data outputs (active-Low), inver.

74ABT5074 Features

* Metastable immune characteristics

* Pin compatible with 74F74 and 74F5074

* Typical fMAX = 200MHz

* Output skew guaranteed less than 2.0ns

* High source current (IOH = 15mA) ideal for clock driver applications PIN CONFIGURATION RD0 D0 CP0 SD0 Q0 Q0 GND 1 2

74ABT5074_PhilipsSemiconductors.pdf