* Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications supporting DDR 200/266/300/333 PIN CONFIGURATION GND 1 Y0 2 Y0 3 VDDQ 4 Y1 5 Y1 6 GND 7 GND 8 Y2 9 Y2 10 VDDQ 11 SCL 12 CLK 13 CLK 14 VDDI2C 15 AVDD 16 AGND 17 GND 18 Y3 19 Y3 20 VDDQ 21 48 GND 47 Y5 46 Y5 45 V
PCK2057
95.18 KB
70 - 190 mhz i2c differential 1:10 clock driver.
INTEGRATED CIRCUITS PCK2057 70 190 MHz I2C differential 1:10 clock driver Product data Supersedes data of 2001 May 09 File under Integrated.
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