PCK2057 Datasheet - NXP

PCK2057 70 - 190 MHz I2C differential 1:10 clock driver

The PCK2057 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs and one differential pair of feedback clock outputs. The clock outputs are controlled by the clock inputs (CLK, CLK), the f.

PCK2057 Features

* Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications supporting DDR 200/266/300/333 PIN CONFIGURATION GND 1 Y0 2 Y0 3 VDDQ 4 Y1 5 Y1 6 GND 7 GND 8 Y2 9 Y2 10 VDDQ 11 SCL 12 CLK 13 CLK 14 VDDI2C 15 AVDD 16 AGND 17 GND 18 Y3 19 Y3 20 VDDQ 21 48 GND 47 Y5 46 Y5 45 V

PCK2057_PhilipsSemiconductors.pdf