* Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications PIN CONFIGURATION GND 1 Y0 2 Y0 3 VDDQ 4 Y1 5 Y1 6 GND 7 GND 8 Y2 9 Y2 10 VDDQ 11 VDDQ 12 CLK 13 CLK 14 VDDQ 15 AVCC 16 AGND 17 GND 18 Y3 19 Y3 20 VDDQ 21 Y4 22 Y4 23 GND 24 48 GND 47 Y5 46 Y5 45 VDDQ 44 Y6 43
PCK857
62.59 KB
66-150mhz phase locked loop differential 1:10 sdram clock driver.
INTEGRATED CIRCUITS PCK857 66 150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver Preliminary specification 1998 Dec 10 Philips Se.
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