PCK857 Datasheet - NXP

PCK857 66-150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver

Zero delay buffer to distribute an SSTL differential clock input pair to 10 SSTL_2 differential output pairs. Outputs are slope controlled. External feedback pin for synchronization of the outputs to the input. A CMOS style Enable/Disable pin is provided for low power disable. SW00358 ORDERING INF.

PCK857 Features

* Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications PIN CONFIGURATION GND 1 Y0 2 Y0 3 VDDQ 4 Y1 5 Y1 6 GND 7 GND 8 Y2 9 Y2 10 VDDQ 11 VDDQ 12 CLK 13 CLK 14 VDDQ 15 AVCC 16 AGND 17 GND 18 Y3 19 Y3 20 VDDQ 21 Y4 22 Y4 23 GND 24 48 GND 47 Y5 46 Y5 45 VDDQ 44 Y6 43

PCK857 Datasheet (62.59 KB)

PCK857 Datasheet Preview — Preview of PCK857 PDF

Datasheet Details

Part number:

PCK857

Manufacturer:

NXP ↗

File Size:

62.59 KB

Description:

66-150mhz phase locked loop differential 1:10 sdram clock driver.

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TAGS

PCK857 66-150MHz Phase Locked Loop Differential 110 SDRAM Clock Driver NXP

PCK857 Distributor