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NT5DS32M8ES Datasheet - Nanya

NT5DS32M8ES Commercial and Industrial Consumer DDR 256Mb SDRAM

Nanya 256Mb SDRAMs is a high-speed CMOS Double Data Rate SDRAM containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. It uses a double-data-rate architecture to achieve high speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an i.

NT5DS32M8ES Features

* JEDEC DDR Compliant - Differential clock inputs (CK and ) - DLL aligns DQ and DQS transition with CK transitions - 2n Prefetch Architecture - DQS is edge-aligned with data for reads and center-aligned with data for WRITEs - DQ and DM referenced to both edges of DQS - tRAS lockout (tRAP = tR

NT5DS32M8ES-Nanya.pdf