Description
The ’97 contains a synchronous 6-stage binary counter and six decoding gates that serve to gate the clock through to the output at a sub-multiple of the input frequency The output pulse rate relative to the clock frequency is determined by signals applied to the Select (S0
S5) inputs Both true and complement outputs are available along with an enable input for each A Count Enable input and a Terminal Count output are provided for cascading two or more packages An asynchronous Master Rese
Features
5497_NationalSemiconductor.pdf
