Datasheet4U Logo Datasheet4U.com

DM74LS109A

Dual Positive-Edge-Triggered J-K Flip-Flops

DM74LS109A Features

* Y Alternate Military Aerospace device (54LS109) is available Contact a National Semiconductor Sales Office Distributor for specifications Connection Diagram Dual-In-Line Package TL F 6368

* 1 Order Number 54LS109DMQB 54LS109FMQB DM54LS109AJ DM54LS109AW DM74LS109AM or DM74LS109AN See NS P

DM74LS109A General Description

This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs The J and K data is accepted by the flip-flop on the rising edge of the clock pulse The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of.

DM74LS109A Datasheet (135.00 KB)

Preview of DM74LS109A PDF

Datasheet Details

Part number:

DM74LS109A

Manufacturer:

National Semiconductor

File Size:

135.00 KB

Description:

Dual positive-edge-triggered j-k flip-flops.
54LS109 DM54LS109A DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset Clear and Complementary Outputs June 1989 54LS109 DM54LS109A D.

📁 Related Datasheet

DM74LS109A - Dual Positive-Edge-Triggered J-K Flip-Flop (Fairchild Semiconductor)
DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs June 1986 Revised March 2000 DM74LS109A Dual Pos.

DM74LS10 - Triple 3-Input NAND Gate (Fairchild Semiconductor)
DM74LS10 Triple 3-Input NAND Gate August 1986 Revised March 2000 DM74LS10 Triple 3-Input NAND Gate General Description This device contains three in.

DM74LS10 - Triple 3-Input NAND Gates (National Semiconductor)
54LS10 DM54LS10 DM74LS10 Triple 3-Input NAND Gates June 1989 54LS10 DM54LS10 DM74LS10 Triple 3-Input NAND Gates General Description This device cont.

DM74LS107A - Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops (National Semiconductor)
DM54LS107A DM74LS107A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs June 1989 DM54LS107A DM74LS107A .

DM74LS11 - Triple 3-Input AND Gate (Fairchild Semiconductor)
DM74LS11 Triple 3-Input AND Gate August 1986 Revised March 2000 DM74LS11 Triple 3-Input AND Gate General Description This device contains three inde.

DM74LS11 - Triple 3-Input AND Gates (National Semiconductor)
54LS11 DM54LS11 DM74LS11 Triple 3-Input AND Gates June 1989 54LS11 DM54LS11 DM74LS11 Triple 3-Input AND Gates General Description This device contai.

DM74LS112A - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop (Fairchild Semiconductor)
DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised March 2000 DM74.

DM74LS112A - NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS (National Semiconductor)
.. .. .. .

TAGS

DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops National Semiconductor

Image Gallery

DM74LS109A Datasheet Preview Page 2 DM74LS109A Datasheet Preview Page 3

DM74LS109A Distributor