DS90UR241 Description
www.DataSheet4U.com DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer PRELIMINARY September 2006 DS90UR241/DS90UR124.
The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information.
DS90UR241 Features
* pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. Using National Semiconductor’s proprietary random lock, the Serializer’s parallel data are randomized to the Deserializer without the need of RE
DS90UR241 Applications
* n LOCK output flag to ensure data integrity at Receiver side n Balanced TSETUP/THOLD between RCLK and RDATA on Receiver side n Adjustable PTO (progressive turn-on) LVCMOS outputs on Receiver to minimize EMI and SSO effects n @Speed BIST to validate link integrity n All LVCMOS inputs and control pins
📁 Related Datasheet
📌 All Tags
