MC100LVEL30 - Triple D Flip-Flop

ON Semiconductor

MC100LVEL30 Datasheet Preview — Preview of MC100LVEL30 PDF

Datasheet Details

Part number	MC100LVEL30
Manufacturer	ON Semiconductor ↗
File Size	131.03 KB
Description	Triple D Flip-Flop
Datasheet	MC100LVEL30_ONSemiconductor.pdf

MC100LVEL30 Product details

Description

The MC100LVEL30 is a triple master-slave D flip-flop with differential outputs.Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the clock input.In addition to a common Set input individual Reset inputs are provided for each flip-flop.Both the Set and Reset inputs function asynchronous and overriding with respect to the clock inputs.

Features

1200 MHz Minimum Toggle Frequency.
450 ps Typical Propagation Delays.
ESD Protection: > 2 kV Human Body Model.
The 100 Series Contains Temperature Compensation.
PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V.
NECL Mode Operating Range: VCC = 0 V with VEE =.
3.0 V to.
3.8 V.
Internal Input 75 kW Pulldown Resistors.
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test.
Moisture Sens.

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Other Datasheets by ON Semiconductor

MC100LVEL34 - Clock Generation Chip
MC100LVEL38 - Clock Generation Chip
MC100LVEL05 - 2-Input Differential AND/NAND
MC100LVEL13 - Dual 1:3 Fanout Buffer
MC100LVEL14 - 1:5 Clock Distribution Chip
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Published: Apr 26, 2005 |