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MC100LVELT23 - Dual Differential LVPECL to TTL Translator

Datasheet Summary

Description

LVTTL translator.

Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required.

Features

  • 2.0 ns Typical Propagation Delay.
  • Maximum Frequency > 180 MHz.
  • Differential LVPECL Inputs.
  • PECL Mode Operating Range:VCC = 3.0 V to 3.8 V with GND = 0 V.
  • 24 mA LVTTL Outputs.
  • Flow Through Pinouts.
  • Internal Pulldown and Pullup Resi.

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Datasheet preview – MC100LVELT23

Datasheet Details

Part number MC100LVELT23
Manufacturer ON Semiconductor
File Size 147.53 KB
Description Dual Differential LVPECL to TTL Translator
Datasheet download datasheet MC100LVELT23 Datasheet
Additional preview pages of the MC100LVELT23 datasheet.

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Full PDF Text Transcription

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MC100LVELT23 3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator Description The MC100LVELT23 is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the LVELT23 makes it ideal for applications which require the translation of a clock and a data signal. The LVELT23 is available in only the ECL 100K standard. Since there are no LVPECL outputs or an external VBB reference, the LVELT23 does not require both ECL standard versions. The LVPECL inputs are differential. Therefore, the MC100LVELT23 can accept any standard differential LVPECL input referenced from a VCC of +3.3 V. Features • 2.
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