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MC10E151 - 6-BIT D REGISTER

Datasheet Summary

Description

master-slave flip-flops with differential outputs.

Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 (or both) go HIGH.

The asynchronous Master Reset (MR) makes all Q outputs go LOW.

Features

  • 1100 MHz Min. Toggle Frequency.
  • Differential Outputs.
  • Asynchronous Master Reset.
  • Dual Clocks.
  • PECL Mode Operating Range:.
  • VCC = 4.2 V to 5.7 V with VEE = 0 V.
  • NECL Mode Operating Range:.
  • VCC = 0 V with VEE =.
  • 4.2 V to.
  • 5.7 V.
  • Internal Input 50 kW Pulldown Resistors.
  • ESD Protection:.
  • Human Body Model; > 2 kV.
  • Machine Model; > 200 V.
  • Meets or Exceeds JEDEC Standard.

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Datasheet preview – MC10E151

Datasheet Details

Part number MC10E151
Manufacturer ON Semiconductor
File Size 141.41 KB
Description 6-BIT D REGISTER
Datasheet download datasheet MC10E151 Datasheet
Additional preview pages of the MC10E151 datasheet.

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Full PDF Text Transcription

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MC10E151, MC100E151 5 V ECL 6‐Bit D Register Description The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 (or both) go HIGH. The asynchronous Master Reset (MR) makes all Q outputs go LOW. The 100 Series contains temperature compensation. Features • 1100 MHz Min. Toggle Frequency • Differential Outputs • Asynchronous Master Reset • Dual Clocks • PECL Mode Operating Range: ♦ VCC = 4.2 V to 5.7 V with VEE = 0 V • NECL Mode Operating Range: ♦ VCC = 0 V with VEE = −4.2 V to −5.
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