NB3N51044 Datasheet - ON Semiconductor

NB3N51044 Quad HCSL / LVDS Clock Generator

Table 1. PIN DESCRIPTION Pin # Pin Name Type Description 1 REF_SEL Input LVCMOS/ LVTTL level input to select input reference source. Pulldown with crystal as default reference input source. 2 REF_IN Input 25 MHz single *ended reference input clock. 3 VDD 4 GND Power Ground Positi.

NB3N51044 3.3 V, Crystal to 100 MHz / 125 MHz Quad HCSL / LVDS Clock Generator The NB3N51044 is a precision, low phase noise clock generator that supports PCI Express and sRIO clock requirements. The device accepts a 25 MHz fundamental mode parallel resonant crystal or a 25 MHz single ended reference clock signal and generates four differential HCSL/LVDS outputs (See Figure 10 for LVDS interface) of 100 MHz or 125 MHz clock frequency based on frequency select input F_SEL. NB3N51044 is configur.

NB3N51044 Features

* Uses 25 MHz Fundamental Crystal or Reference Clock Input

* Four Low Skew HCSL or LVDS Outputs

* Output Frequency Selection of 100 MHz or 125 MHz

* Individual OE Tri

* States Outputs

* Master Reset and BYPASS Modes

* PCIe Gen 1, Gen 2, Gen 3 Com

NB3N51044-ONSemiconductor.pdf