NB3N51054 Datasheet - ON Semiconductor

NB3N51054 Quad HCSL / LVDS Clock Generator

Pin # Pin Name Type 1 CLK2 HCSL or LVDS output Description Noninverted clock output. (For LVDS levels see Figure 4) 2 CLK2 HCSL or LVDS Inverted clock output. (For LVDS levels see Figure 4) output 3 GND Ground Power supply ground 0 V. This pin provides GND return path for the device. .

NB3N51054 3.3 V, Crystal to 100 MHz Quad HCSL/LVDS PCIe Clock Generator The NB3N51054 is a precision, low phase noise clock generator that supports PCI Express requirements. The device accepts a 25 MHz fundamental mode parallel resonant crystal or a 25 MHz reference clock signal and generates four differential HCSL/LVDS outputs (See Figure 7 for LVDS interface) at 100 MHz clock frequency with maximum skew of 40 ps. Through I2C interface, NB3N51054 provides selectable spread spectrum options of.

NB3N51054 Features

* Uses 25 MHz Fundamental Crystal or Reference Clock Input

* Four Low Skew HCSL or LVDS Outputs

* I2C Support with Read Back Capability

* Spread of

* 0.35%,

* 0.5% and No Spread

* Individual Output Enable/Disable Control through I2C

* PCI

NB3N51054 Datasheet (162.85 KB)