NB4N11S - 3.3V 1:2 AnyLevel Input to LVDS Fanout Buffer /Translator
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EP Name Q0 Q0 Q1 Q1 VCC NC VEE VEE VTD D D VTD VCC VCC VCC VCC * LVPECL, CML, LVDS, LVCMOS, LVTTL LVPECL, CML, LVDS, LVCMOS, LVTTL * * * * * I/O LVDS Output LVDS Output LVDS Output LVDS Output * Descri
NB4N11S 3.3 V 1:2 AnyLevel™ Input to LVDS Fanout Buffer / Translator The NB4N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevelTM input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS.
These signals will be translated to LVDS and two identical copies of Clock or Data will be distributed, operating up to 2.0 GHz or 2.5 Gb/s, respectively.
As such, the NB4N11S is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or Data distribution applications.
The NB4N11S has a
NB4N11S Features
* www.DataSheet4U.com http://onsemi.com MARKING DIAGRAM
* 16 1 1 QFN
* 16 MN SUFFIX CASE 485G NB4N 11S ALYW A L Y W = Assembly Location = Wafer Lot = Year = Work Week
* Maximum Input Clock Frequency > 2.0 GHz Maximum
