NBSG53A Datasheet - ON Semiconductor

NBSG53A 2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider

Pin Name I/O Description 1 VTCLK * Internal 50 W Termination Pin. See Table 4. 2 CLK ECL, CML, Inverted Differential Input. LVCMOS, LVDS, LVTTL Input 3 CLK ECL, CML, Noninverted Differential Input. LVCMOS, LVDS, LVTTL Input 4 VTCLK * Internal 50 W Termination Pin. .

NBSG53A 2.5 V/3.3 V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS The NBSG53A is a multi-function differential D flip-flop (DFF) or fixed divide by two (DIV/2) clock generator. This is a part of the GigaCommt family of high performance Silicon Germanium products. A strappable control pin is provided to select between the two functions. The device is housed in a low profile 4x4 mm 16-pin Flip-Chip BGA (FCBGA) or a 3x3 mm 16 pin QFN package. The NBS.

NBSG53A Features

* Maximum Input Clock Frequency (DFF) > 8 GHz Typical (See Figures 3, 5, 7, 9, and 10)

* Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical (See Figures 4, 6, 8, 9, and 10)

* 210 ps Typical Propagation Delay (OLS = FLOAT)

* 45 ps Typical Rise and Fall Times (OLS =

NBSG53A Datasheet (162.14 KB)