NBSG14 Datasheet (ON Semiconductor) - SiGe Differential 1:4 Clock/Data Driver

NBSG14, SiGe Differential 1:4 Clock/Data Driver

MARKING DIAGRAMS * The NBSG14 is a 1 *to *4 clock/data distribution chip, optimized for ultra *low skew and jitter.

Inputs incorporate internal 50 W termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS.

Outputs are RSECL (Red

NBSG14 Features

* SG 14 ALYW FCBGA

* 16 BA SUFFIX CASE 489

* Maximum Input Clock Frequency up to 12 GHz Typical Maximum Input Data Rate up to 12 Gb/s Typical 30 ps Typical Rise and Fall Times 125 ps Typical Prop