NBSG16M - 2.5V/3.3V Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer

Product Overview

ON Semiconductor

Part number	NBSG16M
Manufacturer	ON Semiconductor
File Size	126.71 KB
Description	2.5V/3.3V Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer
Datasheet	NBSG16M Datasheet
Additional preview pages of the NBSG16M datasheet.

receiver/driver/translator buffer.

The device is functionally equivalent to the EP16, LVEP16, or SG16 devices with CML output structure and lower EMI capabilities.

Maximum Input Clock Frequency > 10 GHz Typical.
Maximum Input Data Rate > 10 Gb/s Typical.
120 ps Typical Propagation Delay.
35 ps Typical Rise and Fall Times.
Positive CML Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V.
Negative CML Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE =.
2.375 V to.
3.465 V.
CML Output Level; 400 mV Peak-to-Peak Output with 50 W Receiver R.

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Published: Nov 30, 2025 |