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NBSG16M - 2.5V/3.3V Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer

General Description

receiver/driver/translator buffer.

The device is functionally equivalent to the EP16, LVEP16, or SG16 devices with CML output structure and lower EMI capabilities.

Key Features

  • Maximum Input Clock Frequency > 10 GHz Typical.
  • Maximum Input Data Rate > 10 Gb/s Typical.
  • 120 ps Typical Propagation Delay.
  • 35 ps Typical Rise and Fall Times.
  • Positive CML Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V.
  • Negative CML Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE =.
  • 2.375 V to.
  • 3.465 V.
  • CML Output Level; 400 mV Peak-to-Peak Output with 50 W Receiver R.

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Datasheet Details

Part number NBSG16M
Manufacturer onsemi
File Size 126.71 KB
Description 2.5V/3.3V Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer
Datasheet download datasheet NBSG16M Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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NBSG16M 2.5 V/3.3 V Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer Description The NBSG16M is a differential current mode logic (CML) receiver/driver/translator buffer. The device is functionally equivalent to the EP16, LVEP16, or SG16 devices with CML output structure and lower EMI capabilities. Inputs incorporate internal 50 W termination resistors and accept LVNECL (Negative ECL), LVPECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. The CML output structure contains internal 50 W source termination resistor to VCC. The device generates 400 mV output amplitude with 50 W receiver resistor to VCC. The VBB pin is internally generated voltage supply available to this device only.