Part NBSG16M
Description 2.5V/3.3V Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer
Manufacturer onsemi
Size 126.71 KB
onsemi
NBSG16M

Overview

  • Maximum Input Clock Frequency > 10 GHz Typical
  • Maximum Input Data Rate > 10 Gb/s Typical
  • 120 ps Typical Propagation Delay
  • 35 ps Typical Rise and Fall Times
  • Positive CML Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
  • Negative CML Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V
  • CML Output Level; 400 mV Peak-to-Peak Output with 50 W Receiver Resistor to VCC
  • 50 W Internal Input and Output Termination Resistors
  • Compatible with Existing 2.5 V/3.3 V LVEP, EP, LVEL and SG Devices
  • VBB Reference Voltage Output