Description
PCS3P623Z05A, PCS3P623Z05B, PCS3P623Z09A, PCS3P623Z09B Product Preview TIMING SAFEt Peak EMI Reduction IC .
PCS3P623Z05/09 is a versatile, 3.
delay buffer designed
to distribute Timing.
Safe clocks with Peak EMI reduction.
Features
* Clock Distribution with Timing
* Safe Peak EMI Reduction
* Input Frequency Range: 20 MHz
* 50 MHz
* Multiple Low Skew Timing
* Safe Outputs:
PCS3P623Z05: 5 Outputs PCS3P623Z09: 9 Outputs
* External Input
* Output Delay Control Option
Applications
* requiring zero input
* output delay, all outputs, including DLY_CTRL, must be equally loaded. Even if DLY_CTRL is not used, it must have a capacitive load equal to that on other outputs, for obtaining zero input
* output delay. Timing
* Safe Technology Timing
* Safe technolog
