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PI6CV857B 1:10 PLL Clock Driver

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Description

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI6CV857.
PI6CV857B PLL clock device is developed for registered DDR DIMM applications This PLL Clock Buffer is designed for 2.

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Features

* Operating Frequency up to 200 MHz and exceeds PC2700 RDIMM specification
* Distributes one differential clock input pair to ten differential clock output pairs.
* Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2 www. DataSheet4U. com
* Input PWRDWN: LVCMOS
* Outputs (

Applications

* This PLL Clock Buffer is designed for 2.5 VDDQ and 2.5V AVDD operation and differential data input and output levels. The device is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair fe

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