* PLL clock distribution optimized for Double Data Rate SDRAM applications. Distributes one differential clock input pair to ten differential clock output pairs. Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2 Input PWRDWN: LVCMOS www.DataSheet4U.com Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2 Exter
PI6CV857L Datasheet (328.30 KB)
PI6CV857L
Pericom Semiconductor Corporation
328.30 KB
Pll clock driver.
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