* PLL clock distribution optimized for SSTL_2 DDR SDRAM applications. Distributes one differential clock input pair to five differential clock output pairs. Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2 Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2 External feedback pins (FBIN,FBIN) are used to synchr
PI6CV855 Datasheet (303.16 KB)
PI6CV855
Pericom Semiconductor Corporation
303.16 KB
Pll clock driver for 2.5v sstl 2 ddr sdram memory.
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