PI6CV855 Datasheet - Pericom Semiconductor Corporation

PI6CV855 PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory

PI6CV855 PLL clock device is developed for SSTL_DDR SDRAM applications. This PLL Clock Buffer is designed for 2.5 VDDQ and 2.5V AVDD operation and differential data input and output levels. The device is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to five differen.

PI6CV855 Features

* PLL clock distribution optimized for SSTL_2 DDR SDRAM applications. Distributes one differential clock input pair to five differential clock output pairs. Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2 Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2 External feedback pins (FBIN,FBIN) are used to synchr

PI6CV855_PericomSemiconductorCorporation.pdf