74LV107 Datasheet (Philips) - Dual JK flip-flop

74LV107, Dual JK flip-flop

The 74LV107 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT107.

The 74LV107 is a dual negative-edge triggered JK-type flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs.

The J and K inputs must be stable o

74LV107 Features

* Wide operating: 1.0 to 5.5 V

* Optimized for low voltage applications: 1.0 to 3.6 V

* Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

* Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V,

* Typical VOHV (output VOH undershoot) > 2 V at