PCS3P623Z05B Description
May 2008 rev 0.1 Timing-Safe™ Peak EMI reduction IC PCS3P623Z05A/B PCS3P623Z09A/B www.DataSheet4U.com General .PCS3P623Z05B Features
* Clock distribution with Timing-Safe™ Peak EMI Reduction Input frequency range: 20MHz - 50MHz Multiple low skew Timing-safe™ Outputs: PCS3P623Z05: 5 Outputs PCS3P623Z09: 9 OutputsPCS3P623Z05B Applications
* requiring zero input-output delay, all outputs, including DLY_CTRL, must be equally loaded. Even if DLY_CTRL is not used, it must have a capacitive load equal to that on other outputs, for obtaining zeroinput-output delay. Timing-Safe™ technology Timing-Safe™ technology is the ability to modulate a
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