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HYB18T512161B2F-20 Datasheet - Qimonda AG

HYB18T512161B2F-20 512-Mbit x16 DDR2 SDRAM

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchrono.
June 2007 www.DataSheet4U.com HYB18T512161B2F 20/25 512-Mbit x16 DDR2 SDRAM DDR2 SDRAM RoHS compliant Internet Data Sheet Rev. 1.1 Internet Data Sheet www.DataSheet4U.com HYB18T512161B2F 20/25 512-Mbit Double-Data-Rate-Two SDRAM HYB18T512161B2F 20/25 Revision History: 2007-06, Rev. 1.1 Page All Subjects (major changes since last revision) Typo Changes We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? .

HYB18T512161B2F-20 Features

* The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:

* Data masks (DM) for write data

* 1.8 V ± 0.1V VDD for [

* 20/

* 25]

* 1.8 V ± 0.1V VDDQ for [

* 20/

* 25]

* Posted CAS by programmable additive latency for better

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Datasheet Details

Part number:

HYB18T512161B2F-20

Manufacturer:

Qimonda AG

File Size:

1.30 MB

Description:

512-mbit x16 ddr2 sdram.

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HYB18T512161B2F-20 HYB18T512161B2F-20 512-Mbit x16 DDR2 SDRAM Qimonda AG

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