HYB18T512161BF Datasheet (Qimonda AG) - 512-Mbit x16 DDR2 SDRAM

HYB18T512161BF, 512-Mbit x16 DDR2 SDRAM

latched at the cross point of differential clocks (CK rising and CK falling).

All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion.

A 15-bit address bus for ×16 components is used to convey row, column and bank address information in a RAS-CA

December 2006 www.DataSheet4U.com HYB18T 512161 B F 512-Mbit x16 DDR2 SDRAM DDR2 SDRAM RoHS compliant Internet Data Sheet Rev.

1.43 Internet Data Sheet www.DataSheet4U.com HYB18T512161BF 20/22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM HYB18T512161BF Revision History: 2006-11, Rev.

1.43 Page All 94-101 82-86 All All 9 86 77 - 80 67 71 76 77 78 86 Subjects (major changes since last revision) Adapted internet edtion added chapter 7 explaining AC timing measurement condition (refere

HYB18T512161BF Features

* The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:

* Commands entered on each positive clock edge, data and

* 1.8 V ± 0.1V VDD for [

* 25/

* 28/

* 33]

* 2.0 V ± 0.1V VDD for [

* 20/

* 22] data mask are referenced to both