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HYB18T512800B

512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512800B Features

* The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:

* Off-Chip-Driver impedance adjustment (OCD) and On

* 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality

* DRAM organizations with 4 and 8

HYB18T512800B General Description

latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion. A 16-bit address bus for ×4 and ×8 organized components and a 15-bit address bus for ×16 components is used to.

HYB18T512800B Datasheet (3.73 MB)

Preview of HYB18T512800B PDF

Datasheet Details

Part number:

HYB18T512800B

Manufacturer:

Qimonda

File Size:

3.73 MB

Description:

512-mbit double-data-rate-two sdram.
May 2007 HYB18T512400B[C/F] HYB18T512800B[C/F] HYB18T512160B[C/F] 512-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products www.DataShe.

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HYB18T512800B 512-Mbit Double-Data-Rate-Two SDRAM Qimonda

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