HYB18T512800B, HYB18T512400B Datasheet - Qimonda

HYB18T512800B 512-Mbit Double-Data-Rate-Two SDRAM

latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion. A 16-bit address bus for ×4 and ×8 organized components and a 15-bit address bus for ×16 components is used to.

May 2007 HYB18T512400B[C/F] HYB18T512800B[C/F] HYB18T512160B[C/F] 512-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products www.DataSheet4U.com Internet Data Sheet Rev. 1.1 Internet Data Sheet HYB18T512[40/80/16]0B[C/F] 512-Mbit Double-Data-Rate-Two SDRAM HYB18T512400B[C/F], HYB18T512160B[C/F], HYB18T512800B[C/F] Revision History: 2007-05, Rev. 1.1 Page All All All Subjects (major changes since last revision) Adapted internet edition Added more product types Qimonda template u.

HYB18T512800B Features

* The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:

* Off-Chip-Driver impedance adjustment (OCD) and On

* 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality

* DRAM organizations with 4 and 8

HYB18T512400B_Qimonda.pdf