HYB18TC256160AF - 256-Mbit Double-Data-Rate-Two SDRAM

Qimonda

Datasheet Details

Part number	HYB18TC256160AF
Manufacturer	Qimonda
File Size	3.45 MB
Description	256-Mbit Double-Data-Rate-Two SDRAM
Datasheet	HYB18TC256160AF_Qimonda.pdf

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.

The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:.
Off-Chip-Driver impedance adjustment (OCD) and.
1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O On-Die-Termination (ODT) for better signal quality.
DRAM organizations with 8,16 data in/outputs.
Auto-Precharge operation for read and write bursts.
Double Data Rate architecture: two data transfers per.
Auto-Refresh, Self-Refresh and power saving Powerc.

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Published: Sep 10, 2008 |