HYB18TC1G160AF Datasheet - Qimonda

HYB18TC1G160AF 1-Gbit DDR2 SDRAM

CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion. A 17 bit address bus for ×4 and ×8 organised components and a 16 bit address bus for ×16 components is used to convey row, column and bank address information in aRASCAS multi.

September 2006 HYB18T C1G 80 0 AF HYB18T C1G 16 0 AF 1-Gbit DDR2 SDRAM DDR2 SDRAM RoHS Compliant Internet Data Sheet Rev. 1.11 Free Datasheet http://www.datasheet4u.com/ Internet Data Sheet HYB18TC1G[80/16]0AF 1-Gbit DDR2 SDRAM HYB18TC1G800AF, HYB18TC1G160AF Revision History: 2006-09, Rev. 1.11 Page All All 102 Subjects (major changes since last revision) Qimonda update Adapted internet edition Modified AC Timing Parameters Added more speedsorts: HYB18TC1G800AF-5, HYB18TC1G800AF-3.7, HYB1.

HYB18TC1G160AF Features

* The 1-Gbit Double-data-Rate SDRAM offers the following key features:

* Off-Chip-Driver impedance adjustment (OCD) and On

* 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality.

* DRAM organizations with 8, 16 data i

HYB18TC1G160AF Datasheet (3.01 MB)