HYB18TC1G800BF Datasheet (Qimonda) - 1-Gbit Double-Data-Rate-Two SDRAM

HYB18TC1G800BF, 1-Gbit Double-Data-Rate-Two SDRAM

latched at the cross point of differential clocks (CK rising and CK falling).

All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion.

A 17 bit address bus for ×8 organised components and a 16 bit address bus for ×16 components is used to convey

July 2007 HYB18T C1G 80 0 BF HYB18T C1G 16 0 BF 1-Gbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev.

1.21 Free Datasheet http://www.datasheet4u.com/ Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM HYB18TC1G800BF, HYB18TC1G160BF Revision History: 2007-07, Rev.

1.21 Page All 14 136 Subjects (major changes since last revision) Adapted internet edition Corrected Table 9: Added Ball B2 and B8 Corrected package outline Editorial

HYB18TC1G800BF Features

* The 1-Gbit Double-Data-Rate-Two SDRAM offers the following key features:

* Off-Chip-Driver impedance adjustment (OCD) and On

* 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality.

* DRAM organizations with 8 and 16