Description
November 2007 www.DataSheet4U.com HYB18T C25680 0 AF HYB18T C25616 0 AF HYI18TC256800AF HYI18TC256160AF 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDR.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Features
* The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
* Off-Chip-Driver impedance adjustment (OCD) and
* 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O On-Die-Termination (ODT) for better signal quality
* DRAM organizations with 8,16 d
