HYB25D512400CE Datasheet - Qimonda

HYB25D512400CE (HYB25D512xx0Cx) DDR SDRAM

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bit.

September 2006 HYB25D512400C[E/T/F/C](L) HYB25D512800C[E/T/F/C](L) HYB25D512160C[E/T/F](L) www.DataSheet4U.com DDR SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.31 Internet Data Sheet HYB25D512[400/160/800]C[E/T/F/C](L) 512-Mbit Double-Data-Rate SDRAM HYB25D512400C[E/T/F/C](L), HYB25D512800C[E/T/F/C](L), HYB25D512160C[E/T/F](L) Revision History: 2006-09, Rev. 1.31 Page www.DataSheet4U.com Subjects (major changes since last revision) Qimonda update Adapted internet edition All .

HYB25D512400CE Features

* Burst Lengths: 2, 4, or 8 CAS Latency: 2, 2.5, 3 Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes RAS-lockout supported tRAP=tRCD 7.8 µs Maximum Aver

HYB25D512400CE_Qimonda.pdf