Datasheet Details
Part number:
HYB25D512400DE
Manufacturer:
Qimonda
File Size:
2.42 MB
Description:
512M DDR SDRAM
Features
* Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for reads and is center-aligned with data for writes Differential clock inputs (CK and
HYB25D512400DE, 512M DDR SDRAM
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an Active command, which is then followed by a Read or Write command.
The address bit
July 2008 www.DataSheet4U.com HYB25D512400D[E/F/T] HY[B/I]25D512800D[C/E/F/T](L) HY[B/I]25D512160D[C/E/F/T](L) 5 1 2 - M b i t D o u b l e - D a t a - R a t e SD R A M DDR SDRAM Internet Data Sheet Rev.
1.01 Internet Data Sheet www.DataSheet4U.com HY[B/I]25D512[40/80/16]0D[C/E/F/T](L) 512-Mbit Double-Data-Rate SDRAM Revision History: Rev.
1.01, 2008-07 All Page 29 Page 33 All Adapted internet edition Changed tCK.MAX at CL=3 for -5 speed Added new IDD values New data sheet Previous Revisi
HYB25D512400DE Distributor
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