HYB25DC256163CE-4 Datasheet - Qimonda

HYB25DC256163CE-4 256-Mbit Double-Data-Rate SGRAM

The 256-Mbit Double-Data-Rate SGRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The 256-Mbit Double-Data-Rate SGRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate archite.

HYB25DC256163CE-4 HYB25DC256163CE-5 HYB25DC256163CE-6 256-Mbit Double-Data-Rate SGRAM Green Product January 2007 Internet Data Sheet Rev. 1.1 Internet Data Sheet HYB25DC256163CE-4, HYB25DC256163CE-5, HYB25DC256163CE-6 Revision History: 2007-01, Rev. 1.1 Page Subjects (major changes since last revision) All Adapted internet edition All Added new speedsort -4 Previous Revision: 2007-01, Rev. 1.0 HYB25DC256163CE 256-Mbit Double-Data-Rate SGRAM We Listen to Your Comments Any information wi.

HYB25DC256163CE-4 Features

* of the product family HYB25DC256163CE and the ordering information. 1.1 Features

* Double data rate architecture: two data transfers per clock cycle

* Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver

* DQS is

HYB25DC256163CE-4 Datasheet (677.92 KB)