HYB25DC512800B Datasheet - Qimonda

HYB25DC512800B 512-Mbit Double-Data-Rate SDRAM

The 512-Mbit Double-Data-Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. The 512-Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate archite.

www.datasheet4u.com April 2007 HYB25DC512800B[E/F] HYB25DC512160B[E/F] 512-Mbit Double-Data-Rate SDRAM DDR SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.2 www.datasheet4u.com Internet Data Sheet HYB25DC512[80/16]0B[E/F] Double-Data-Rate SDRAM HYB25DC512800B[E/F], HYB25DC512160B[E/F] Revision History: 2007-04, Rev. 1.2 Page All All All Subjects (major changes since last revision) Adapted internet edition Editorial changes Qimonda template update Previous Revision: 2006-09, Rev.

HYB25DC512800B Features

* This chapter lists all main features of the product family HYB25DC512[80/16]0B[E/F] and the ordering information. Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver DQ

HYB25DC512800B Datasheet (1.97 MB)