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HYB25DC512800BF

512-Mbit Double-Data-Rate SDRAM

HYB25DC512800BF Features

* This chapter lists all main features of the product family HYB25DC512[80/16]0B[E/F] and the ordering information. Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver DQ

HYB25DC512800BF General Description

The 512-Mbit Double-Data-Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. The 512-Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate archite.

HYB25DC512800BF Datasheet (1.97 MB)

Preview of HYB25DC512800BF PDF

Datasheet Details

Part number:

HYB25DC512800BF

Manufacturer:

Qimonda

File Size:

1.97 MB

Description:

512-mbit double-data-rate sdram.
www.datasheet4u.com April 2007 HYB25DC512800B[E/F] HYB25DC512160B[E/F] 512-Mbit Double-Data-Rate SDRAM DDR SDRAM RoHS Compliant Products Internet .

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HYB25DC512800BF 512-Mbit Double-Data-Rate SDRAM Qimonda

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