Description
The 256-Mbit Double-Data-Rate SGRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits.
Features
- of the product family HYB25DC256163CE and the ordering information. 1.1 Features.
- Double data rate architecture: two data transfers per clock cycle.
- Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
- DQS is edge-aligned with data for reads and is center-aligned with data for writes.
- Differential clock inputs (CK and CK).
- Four internal banks for concurrent operation.
- Data mask.
